Research & Projects | Manimohan Thiriloganathan

Research Publications

Published at SMACD 2026 (IEEE Xplore) · Accepted at IEEE ITSC 2026.

Published in IEEE XploreFirst AuthorView Paper GitHub

A 2.4 GHz LC-VCO Fractional-N Phase-Locked Loop Open-Source Design in 130-nm BiCMOS

RF IC Design / PLL

SMACD 2026

Dresden, Germany - International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design

Radio frequency (RF) integrated circuit design using the open-source CMOS ecosystem is limited by unreliable passive device models, especially on-chip spiral inductors. This work presents a 2.4 GHz type-II fractional-N PLL in IHP SG13G2 130 nm BiCMOS using a cross-coupled differential LC-VCO with a custom spiral inductor built using an open-source OpenEMS workflow. The optimized inductor achieves 4 nH inductance with a quality factor of 16.8 at 2.45 GHz. The LC-VCO sensitivity is approximately 120 MHz/V, while PLL phase noise is -100.8 dBc/Hz at 1 MHz offset. The complete PLL is implemented using a fully open-source EDA flow, occupying 930 μm × 666 μm (≈ 0.619 mm²) and consuming 12.73 mW — demonstrating the feasibility of RF IC design in an open-source CMOS ecosystem.

Accepted at IEEE ITSC 2026Co-First AuthorEqually ContributedView Paper GitHub

An Embedded Real-Time License Plate Recognition System for Complex Traffic Scenes

Embedded AI / Computer Vision

IEEE Intelligent Transportation Systems Conference (ITSC 2026)

Naples, Italy

This work presents an embedded real-time license plate recognition (LPR) system customised for developing countries with complex, unstructured traffic scenes. The method uses a two-stage pipeline: license plate detection on multi-vehicle images followed by character recognition on the detected plates. Both steps use lightweight convolutional neural networks to balance accuracy and efficiency. The SL-LPR dataset of Sri Lankan road images is introduced, covering diverse vehicle types and traffic conditions typical of developing countries. The LPD model achieves 93.6% mAP and the LPCR model achieves 87.88% plate-level accuracy. Low-bitwidth quantization (Brevitas) and FPGA acceleration (FINN framework) are applied for real-time edge deployment, reaching 11.5 FPS at 87 ms max latency per frame on the Xilinx Kria KV260.

Selected Projects

Final Year ProjectIEEE ITSC 2026FPGA · Radar · Embedded AI

Multi-Lane Speed Measurement Edge Module with License Plate Recognition

Low-cost speed enforcement for Sri Lankan roads: 77 GHz mmWave radar measures each vehicle's speed while quantized neural networks read its license plate in real time on a Kria KV260 FPGA (11.5 FPS).

UNIC-CASS chip layout: top view with fillers and 2.5D view of the 2.4 GHz PLL

2.4 GHz Fractional-N PLL with LC-VCO — IHP SG13G2 130 nm

Silicon TapeoutIEEE CASS UNIC 2026 · Published at SMACD 2026

Type-II ΔΣ fractional-N PLL with a Type-IV LC-VCO and a custom 4 nH spiral inductor (Q ≈ 16.8) modelled with OpenEMS. −100.8 dBc/Hz at 1 MHz, 12.73 mW, 0.619 mm², fully open-source flow.

GitHub IEEE Paper

PFD-CP Type-II ΔΣ Fractional-N PLL Clock Multiplier — IHP SG13G2

Silicon TapeoutIHP OpenMPW · July 2025

11-stage current-starved ring-oscillator VCO, ~50 MHz tunable with zero standby power, taken through layout, DRC/LVS, PEX and post-layout simulation.

PLL GitHub VCO GitHub

Analog IC & Circuit Designs

Academic ProjectAnalog IC Design • Cadence 45 nm · LTspice

Three current-mirror OTA, 3 GHz fully differential LC-VCO, PFD-CP ΔΣ PLL, analog mixers, ring oscillators and a linear power supply.

Analog IC Design Analog Circuits