A 2.4 GHz LC-VCO Fractional-N Phase-Locked Loop Open-Source Design in 130-nm BiCMOS

Read the Paper GitHub Repository arXiv Preprint

Conference

SMACD 2026

Dresden, Germany - International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design

Authors

Manimohan Thiriloganathan, Shenal Ranasinghe, Avishka Herath, Rajinthan Rameshkumar, Hansa Marasinghe, Anjana Viduranga, Gayangana Leelarathne, Kithmin Wickremasinghe

Keywords

Abstract

Radio frequency (RF) integrated circuit design using the open-source CMOS ecosystem is limited by unreliable passive device models, especially on-chip spiral inductors. This work presents a 2.4 GHz type-II fractional-N PLL in IHP SG13G2 130 nm BiCMOS using a cross-coupled differential LC-VCO with a custom spiral inductor built using an open-source OpenEMS workflow. The optimized inductor achieves 4 nH inductance with a quality factor of 16.8 at 2.45 GHz. The LC-VCO sensitivity is approximately 120 MHz/V, while PLL phase noise is -100.8 dBc/Hz at 1 MHz offset. The complete PLL is implemented using a fully open-source EDA flow, occupying 930 μm × 666 μm (≈ 0.619 mm²) and consuming 12.73 mW — demonstrating the feasibility of RF IC design in an open-source CMOS ecosystem.

Key Specifications & Results

TechnologyIHP SG13G2 130 nm BiCMOS

Target Frequency2.4 GHz ISM Band (BLE)

VCO TopologyCross-coupled differential LC-VCO (Type-IV)

Inductor4 nH, Q = 16.8 at 2.45 GHz (3-turn octagonal spiral on TopMetal2)

VCO Tuning Range2.4–2.48 GHz (>3.3%)

VCO Sensitivity (KVCO)~120 MHz/V

PLL Phase Noise-100.8 dBc/Hz @ 1 MHz offset

Reference Spur-40.2 dBc

Total Area930 μm × 666 μm ≈ 0.619 mm²

Power Consumption12.73 mW

EDA ToolsXschem, ngspice, KLayout, OpenEMS (FDTD EM solver)

System Architecture

The PLL consists of five main blocks: Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), LC cross-coupled VCO, and a programmable fractional-N divider based on a Delta-Sigma (ΔΣ) modulator. The divider chain includes a 4/5 dual-modulus prescaler, a Mod-7 synchronous counter, a duty cycle corrector, a 9-bit shift register, and a first-order digital DSM that pushes quantization noise beyond the loop bandwidth.

Design Gallery

Figures from the project repository on GitHub. Select an image to open it at full size.

PLL architecture: PFD, charge pump, loop filter, LC-VCO and ΔΣ fractional-N divider

Integrated top-level schematic in Xschem

PLL layout with the custom 4 nH octagonal spiral inductor (2.5D view)

Integrated PLL testbench waveforms (ngspice)

Final UNIC-CASS chip: the PLL inside the pad ring

Presenting the paper at SMACD 2026, Dresden

Key Novelty

To the best of the authors' knowledge, this is the first-ever fully open-source CMOS PLL design with an integrated on-chip spiral inductor. The spiral inductor was modelled using a parametric OpenEMS FDTD workflow with automated parameter sweeps, enabling reproducible RF component development without proprietary EM solvers.

My Contributions

Lead author — project planning, direction, and overall system integration
Integrated full PLL simulation flow using open-source EDA tools (Xschem, ngspice, KLayout)
Layout design of all PLL blocks including DRC and LVS verification
LC-VCO architecture design and implementation with custom OpenEMS spiral inductor optimisation workflow
Spiral inductor parametric design: 3-turn octagonal geometry on TopMetal2, co-optimised for L = 4 nH and Q > 16 at 2.45 GHz

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