Analog Tapeout Design — PFD-CP Type-II Fractional-N PLL Clock Multiplier in IHP SG13G2
Department
Department of Electronic and Telecommunication Engineering, University of Moratuwa
Supervisor & Instructor
Dr. Thayaparan Subramaniam (PhD) · Kithmin Wickremasinghe (MASc)
Team Members
Project Overview
This project implements a charge-pump (CP) based Type-II Phase-Locked Loop (PLL) system in the IHP SG13G2 130 nm BiCMOS technology node, designed to generate programmable output frequencies from a stable 10 MHz reference input. The architecture uses a Voltage-Controlled Oscillator (VCO) together with two 3-bit programmable Frequency Dividers (FDs) to achieve a tunable output frequency.
The Feedback Divider (M) divides the VCO output by a 3-bit integer M, locking the VCO to f_vco = M × f_ref. The Output Divider (N) then produces f_out = f_vco / N = (M / N) × f_ref. With M and N configurable from 1 to 7, the theoretical frequency range spans 1.428 MHz to 70 MHz; VCO constraints limit the practical range to 1.428 MHz to 30 MHz. The complete design was submitted for silicon fabrication via the IHP OpenMPW program (July 2025 edition).
Specifications
| Parameter | Value |
|---|---|
| Reference Frequency | 10 MHz |
| Fractional Division Ratio | 1/7 to 3 |
| Output Frequency Range | 1.428 MHz to 30 MHz |
| Supply Voltage | 1.2 V |
| Average Power Consumption | 304.05 µW |
| Output Slew Rate | 1618.55 V/µs |
| Total Area | 400 µm × 400 µm = 160,000 µm² |
| Technology Node | IHP SG13G2 130 nm BiCMOS |
| Pad Size | 60 µm × 60 µm |
| Pad Pitch | 75 µm |
Circuit Design
Phase-Locked Loop (Top Level)
The top-level PLL uses a standard fractional-N architecture where feedback and output frequency dividers set the frequency multiplication ratio with respect to the reference clock. Five main blocks are integrated: PFD, CP, Loop Filter, LC/Ring VCO, and a 3-bit programmable Frequency Divider.
Phase-Frequency Detector (PFD)
The PFD compares the phase of the reference clock ref_clk with the VCO output vco_clk, generating up and down control signals that drive the charge pump to adjust the VCO control voltage.
Charge Pump (CP) — 26.03 µm²
The CP uses two current sources (bias_p and bias_n) switched to the output by the PFD's up/down signals. The nominal current is set by the Bias Generator and is configurable to suit PLL loop dynamics.
Loop Filter — 297.89 µm²
A passive RC loop filter attenuates high-frequency variations in the charge pump output, delivering a stable control voltage to the VCO and setting the loop bandwidth.
Bias Generator — 354.17 µm²
A self-biased current mirror providing roughly supply-independent current for the charge pump. A startup circuit with a diode-connected device on the kick node prevents the circuit from locking into the zero-current state. Based on the tt08-tiny-pll design with an extra resistor added to increase bias_n.
Voltage-Controlled Oscillator (VCO) — 2246.58 µm²
An 11-stage ring oscillator where each stage is a standard-cell inverter with current-limiting transistors in the triode region for frequency tuning. LVT NMOS devices ensure the control voltage operates around mid-supply (~1 V nominal). Dedicated keeper devices disable the VCO during standby (zero static power). Nominal oscillation frequency: ~50 MHz; tuning range: controlled by supply voltage sweep (~10–100 MHz practical).
Frequency Divider (FD) — 715.22 µm²
A 3-bit binary counter followed by three XOR gates to compare the counter with the division ratio input A[2:0]. When the counter equals BIT, DIV_RST immediately resets the counter, producing a maximum division ratio of 7. A DFF output stage ensures a ~50% duty cycle on the output clock. Maximum effective division ratio (CLK_IN to CLK_OUT): 14.
Pre-Layout Simulation Results
VCO Output (Control Voltage = 1 V)
Output frequency of the 11-stage ring VCO at a control voltage of 1 V is approximately 50 MHz. The VCO was characterised across a control voltage sweep to determine the tuning range.
Charge Pump Operation
Simulation confirmed that when the up pulse width exceeds down, the CP output charges gradually, demonstrating correct PFD-CP interaction and loop dynamics.
Frequency Divider (Ratio = 7)
Input: 80 MHz → Output: 5.71 MHz. Confirms correct ÷7 operation and ~50% output duty cycle from the DFF stage.
Integrated PLL (M = 1, N = 1)
Full PLL closed-loop simulation with multiplication factor of 1: output frequency locked to 10.02 MHz, confirming correct loop behaviour.
Layout Design — Block Areas
| Block | Area |
|---|---|
| Charge Pump | 26.03 µm² |
| Loop Filter | 297.89 µm² |
| Bias Generator | 354.17 µm² |
| 11-Stage Ring VCO | 2246.58 µm² |
| 3-Bit Frequency Divider | 715.22 µm² |
| Full PLL (with fillers) | 160,000 µm² |
Full layout dimensions: 400 µm × 400 µm. All pads: 60 µm × 60 µm, pitch 75 µm. Layers span TM2 through M3 for standard pads; TM2–TM1 for RF pads.
Physical Verification (DRC & LVS)
Design Rule Check (DRC) and Layout vs. Schematic (LVS) verification were performed on the complete integrated PLL layout, confirming that the physical layout matches the schematic netlist and satisfies all IHP SG13G2 fabrication design rules.
Post-Layout Verification after PEX
Parasitic extraction (PEX) simulations were run at three multiplication ratios to validate that the PLL locks correctly after accounting for layout parasitics:
| Configuration | Output Frequency |
|---|---|
| M = 1, N = 1 (×1) | 8.03 MHz |
| M = 1, N = 7 (×1/7) | 1.43 MHz |
| M = 3, N = 1 (×3) | 27.71 MHz |
Slight frequency deviation from ideal (e.g., 8.03 MHz vs 10 MHz for ×1) is attributable to VCO tuning-range shift due to extracted parasitics — consistent with expected PEX behaviour in ring-oscillator-based PLLs.
IHP OpenMPW Submission
The complete PLL layout was submitted for silicon fabrication through the IHP OpenMPW program (July 2025 edition). The tapeout submission repository is available at:
TO_July2025 Repository →